1. Technical Field
The disclosure relates to a non-volatile static random access memory cell and a memory circuit.
2. Related Art
Various digital logic circuits, memories and analog circuits are integrated in a system on chip (SOC) in order to greatly improve a circuit operating speed and functions thereof. Along with functional diversification of electronic products, memory capacity is gradually increased. A static random access memory (SRAM) is a memory with a high accessing speed and low operating voltage. However, when the chip enters a standby mode, in order to preserve the stored data, the SRAM has to be continually powered to compensate current leakage, so as to avoid data error and maintain the stored data. In this case, power consumption caused by the current leakage of the SRAM cannot be ignored. As the CMOS technology scaling down, the leakage issue is getting much more serious along with the increased memory capacity, which results in large static power consumption. In order to avoid unnecessary power consumption and maintain the stored data in case of power-off or the standby mode, a non-volatile memory (NVM) can be used, and a power supply of the NVM can be completely cut off to achieve zero power consumption. However, the existing products or products under development of the NVM are not yet up to an operating speed of the SRAM level.
If the SRAM cell 50 is integrated with the NVM device, a novel non-volatile SRAM (NVSRAM) cell is obtained. During a normal operation, only the SRAM part in the NVSRAM cell is used to perform high accessing speed and low-voltage read/write operation. In case of the standby mode or power off, data can be written in the NVM device in advance before the standby mode or power off, then it is unnecessary to supply power to the NVSRAM cells, so as to avoid the power consumption caused by current leakage. To return back to a normal operation, a recall operation is performed to restore the pre-stored data from the NVM device to the SRAM cell 50. Then, the NVSRAM is operated as a general SRAM and is accessed with a high speed, which does not influence a normal operation of the SRAM.
FIG. 1 is a circuit schematic diagram of a conventional NVSRAM, in which resistive switching devices (RSDs) are used as non-volatile storage devices.
Referring to FIG. 1, the NVSRAM is implemented through a conventional six-transistor structure based on a SRAM, in which besides transistors 100 and 102 are respectively coupled to a bit line BL and a complementary bit line BLB, each of inverters 104 and 106 has two transistors (not shown in FIG. 1). Gates of the two transistors 100 and 102 are coupled to a write line WL. The two inverters 104 and 106 are respectively coupled in series between the two transistors 100 and 102.
A storage node Q is connected to a transistor 108 and a resistive-switching device R1, and another storage node QB is connected to a transistor 110 and a resistive-switching device R2 to form a non-volatile storage part, and other terminals of the two resistive-switching devices R1 and R2 are commonly connected to a control line CTRL. Gates of the transistors 108 and 110 are respectively coupled to a switch line SW.
During a read/write operation of the static access memory, a voltage of the switch line SW is set at a low level, so that the transistors 108 and 110 are turned off to block a connection between the SRAM and the resistive-switching devices R1 and R2, and now the SRAM can be accessed according to a general operation method. When information of the storage nodes is backup to the resistive-switching devices, if the non-volatile device is a unipolar device, a voltage level of the switch line SW is increased to 0.7V, and a voltage level of the control line CTRL is increased to 1.8V, so that the resistive-switching device R2 of the storage node (for example, the storage node QB) has a cross voltage for transiting to a low resistance state (LRS), which is referred to as a SET operation. Then, the power can be turned off. During a recall operation, the voltage level of the switch line SW is set to a high level, and a magnitude of a charging current of the storage node is determined according to a resistance magnitude of R1/R2, and a latch circuit formed by the two inverters 104 and 106 latches the voltage level of Q/QB. After the recall operation is ended, the resistive-switching device R2 is written back to the high resistance state, and the voltage level of the switch line SW is 1.2V and the voltage level of the control line CTRL is 1.2V. Then, it returns to the state for the read/write operation of the SRAM. The operation of writing back the device to the high resistance state is also referred to as a RESET operation. If the non-volatile device is a bipolar device, the voltage level of the switch line SW is increased to 1.8V, and the control line CTRL sequentially provides voltage levels of 1.8V and 0V to respectively generate a positive bias for SET operation and a negative bias for RESET operation.
In such conventional structure, besides the transistors 108 and 110 are required, the resistive-switching devices R1 and R2 are required to be connected to the external control line CTRL, which may increase a layout area. Moreover, when the conventional structure of a unipolar resistive-switching device is used, since the voltage level of the switch line SW is required to be adjusted to control storage of the unipolar resistive-switching device, and the RESET operation is performed after the recall operation, a booting time is influenced.